1. Field of the Invention
The present invention relates to a variable-resistance memory device using a variable-resistance device.
2. Description of the Prior Art
In recent years, as a semiconductor technology advances, devices for rewritable applications such as a flash ROM (Read Only Memory) and EEPROM (Electrically Erasable Programmable ROM) have increased in scale and degree of integration and technologically developed. In a system field using semiconductor devices, required device applications are changing. For example, there is a case where a non-volatile memory element and an OTP element are embedded in a device for security purposes, an IC tag, or the like. There is also a growing tendency toward embedding a large-capacity rewritable nonvolatile memory.
In terms of further reducing the area of a floating-gate (FG) nonvolatile memory, such as a typical flash ROM or EEPROM, recent attention has been focused on novel nonvolatile memories. The representatives thereof are numerous, including a FeRAM using a ferroelectric material, a MRAM using magnetism, a PRAM as a phase-change memory, and a variable-resistance memory.
Among these, each of memory elements in the variable-resistance memory has an oxide film using a material having a perovskite structure and a material such as a binary transition metal oxide. By increasing the resistance of the oxide film (referred to as a write or SET operation) or decreasing the resistance thereof (referred to as an erase or RESET operation), the variable-resistance memory element is caused to perform nonvolatile storage.
These variable-resistance memory elements can be disposed between metal layers in vertically and upwardly stacked relation. Therefore, a reduced area and lower cost are expected by a cross point memory cell array in three dimensions.
Biasing conditions related to the write operation and the erase operation to and from the variable-resistance memory and the relationship between biases differ from one material to another. In a majority of materials, positive and negative bipolar biases are mostly used and applied to the both ends of a resistor, but there is a material which allows the use of a unipolar bias. That is, a voltage is applied to only one of the both ends of an resistor element to enable SET/RESET operations to be performed using the potential levels thereof (see, e.g., Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-251378). In the example of Patent Document 1, a feedback controlled control circuit is connected to a memory cell array to establish an equi-potential state in the memory cell array and recognize a variation in current when the selected resistive device is asserted to a reference state.
However, in the variable-resistance memory mentioned above, the potential on a word line is adjusted to be higher than that on a bit line during a selection period to implement selection, while the potential on the bit line is adjusted to be high and the potential on the word line is adjusted to be low during a non-selection period to constitute reverse biases and enhance selectivity. Accordingly, two potential adjusting mechanisms, i.e., a potential adjusting mechanism for the word lines and a potential adjusting mechanism for the bit lines are necessary. This results in the situation where the potential control intricately involves input signals such as an address signal, a data signal, and a command signal.